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ChipPAC Qualification Results
Assembly Site: ChipPAC, Shanghai (CPS)
Package Style: PLCC
| Product Technology Die Dimensions (mil) Lead Count |
Duration | CDP68HC05-C16 CMOS 3.5 124 x 203 44 lead |
CS82C55A96 L7 100 x 106 44 lead |
HSP45240JC-33 CMOS 186 x 222 68 lead |
HSP50210JC-52 CMOS 169 x 156 84 lead |
| HTOL Ta = 125C |
500 hr 1000 hr |
0 / 78 0 / 78 |
0 / 78 0 / 78 |
no boards available |
0 / 77 0 / 77 |
| Temp/Humidity/Bias 1 85C/85%RH |
500 hr 1000 hr |
0 / 78 0 / 78 |
0 / 78 0 / 78 |
no boards available |
0 / 22 (2,b) 0 / 16 (c) |
| Pressure Cooker 1 121C / 100% RH |
96 hr 192 hr |
0 / 78 0 / 78 |
0 / 78 0 / 78 |
0 / 77 (a) - |
0 / 78 - |
| Temperature Cycle 1 -65C to +150C |
500 cyc 1000 cyc |
0 / 78 0 / 78 |
0 / 78 0 / 78 |
0 / 78 0 / 78 |
0 / 78 0 / 78 |
| Temperature Cycle 1 -40C to +125C |
500 cyc 1000 cyc |
0 / 78 0 / 78 |
0 / 78 0 / 78 |
0 / 78 0 / 78 |
0 / 78 0 / 78 |
| High Temp Storage Ta = 150C |
500 hr 1000 hr |
0 / 78 0 / 78 |
0 / 78 0 / 78 |
- 0 / 78 |
- 0 / 78 |
| Post Temp Cycle Bond Pull 1k cycles, -65C to +150C 5 devices, 100% (grams) |
Average Std.Dev. Minimum Maximum |
12.0 3.3 1.2 18.4 |
10.3 2.4 1.3 15.3 |
13.5 1.7 9.8 18.6 |
7.1 1.6 3.9 13.0 |
Notes: 1. 28 & 44 lead PLCC preconditioned to Level 1 per JEDEC 113. 68 & 84 lead PLCC preconditioned to Level 3.
2. Sample size reduced due to socket availability.
Failure Analysis:
a) One invalid failure, not assembly related. Failure anaysis report # IA000323.
b) Ten invalid rejects due to EOS. Initial sample size 32 devices. Falure analysis report # IA000322.
c) Six invalid rejects due to EOS. Failure analysis report # IA000338.