F
Failure Analysis.
Fabrication. In semiconductor manufacturing, fabrication usually refers to the
front-end process of making devices and integrated circuits in semiconductor wafers, but
does not include the package assembly (back-end) stages.
Field Application Engineer. A term used to describe a Intersil
employee specifically engaged in helping customers apply Intersil products in various
circuits and designs.
Intersil's open-architecture design system, providing state-of-the-art capabilities for
schematic capture, design verification and place and route functions based on Intersil
analog, mixed signal, and digital process families. Extremely useful for Intersil and its
customers to develop high-performance standard products and custom designs. The analog
bipolar FASTRACK system won EDN Magazine's Product Innovation of the Year Award in 1990.
A defect in an IC that can cause a failure during operation. Usually caused by
processing defects.
The percent of all possible internal faults a circuit can have that are observable from
the outside of the IC by a functional test vector set. Typically refers to those faults
modelled by a signal stuck to power or ground.
A logic-gate level simulation technique in which the circuit description is modified
(faulted) to correspond to a processing defect, and the simulation is re-run to determine
whether the test program would find this defect. After many faults are simulated, this
gives an indication of the quality (fault coverage) of the test program.
Field Effect Transistor. A solid-state device in which current is
controlled between source and drain terminals by voltage applied to a non-conducting gate
terminal. See also channel, drain, gate and source.
A package having leads that are parallel to the component body. Hermetic flat packs
have leads on two or four sides. Plastic flat packs usually have leads on all four sides
(plastic quad flat pack). Intersil supplies both plastic and hermetic ceramic flat packs
to the military and commercial markets.
Bonding of chips with contact pads, face down, by solder bump connections.
Floorplanning is used at the chip planning stage to efficiently partition the space of
the chip in order to minimize area. It is also used in the early stages of layout to
investigate tradeoffs in pinout, block placement and rotation, and routing area
construction.
A voltage applied across a rectifying junction with a polarity that provides a
low-resistance conducting path. By contrast, reverse bias causes the junction to block
normal current. See P-N junction.
A wafer production and processing plant. Usually used to denote a facility that is
available on a contract basis to companies that do not have wafer fab capability of their
own, or that wish to supplement their own capabilities.
A term used interchangeably with "glass" as in frit or glass-sealed packages
such as CERDIP and CERPACK.
In semiconductor manufacturing, the fabrication process in which the integrated circuit
is formed in and on the wafer. Compare back end.
Fourier Transform Infrared Spectrophotometry.
Final Test Yield. See yieid.
The application of functional input vectors and the corresponding responses that assure
proper operation of a digital IC.
