P
The protective container or housing for an electronic component or die, with external
terminals to provide electrical access to the components inside. Packages provide for
power and signal distribution, power dissipation, and physical and chemical protection of
the circuits.
Tests that measure DC conditions of a chip, such as maximum current, leakage, and
output drive.
Applies to software that analyzes a layout database and determines the capacitance (and
sometimes resistance) of the metal interconnections. These values, which are considered
parasitic because they are determined by the placement of the devices rather than as part
of the design schematics, are then used in logic or circuit simulations.
Parameter Limited Yield. See yield.
Power ASIC. A versatile power BiMOS process technology co-developed by
Intersil and IBM for use in the manufacture of semicustom and ASIC circuits for power
applications. This technology can support voltages in the 60-100V range and currents of
5-10A. Sometimes referred to as "intelligent power".
A layer of insulating material deposited over a wafer or a region of a device to
stabilize and protect the surface against moisture, contamination, and mechanical damage.
Silicon dioxide or silicon nitride are often used for IC passivation.
An electrical component without gain or current-switching capability. Commonly used
when referring to resistors, capacitors and inductors.
Private Branch EXchange. A telecommunications switching facility
or service located on the customer's premises. Intersil SLIC circuits are found in most of
the world's PBX systems. See SLIC.
Personal Computer, usually an IBM PC or compatible. Also an acronym for
Production Control in a manufacturing organization. Can also refer to Printed Circuit when
referencing printed circuit boards (PCBs).
Photo Defect Limited Yield. See defect,
lithography and yield.
Plasma-Enhanced Chemical Vapor
Deposition. CVD with the gases first passing through a plasma. See CVD.
A performance node is a control parameter which has limited influence on reliability
but which does impact the yield, productivity, or other set of economic indices associated
with the product or technology. See control parameter,
critical node, and characterization
node.
Very powerful, advanced, multi-dimensional optimization algorithms are used for
optimizing circuit performance using many different behavior criteria. The result is a
Intersil product that meets all performance specifications with the greatest possible
yield.
Potential Failure Mode and Effects Analysis.
Pin-Grid Array. A packaging technology for high-pin-count
packages. Name derives from the array of pins at the bottom of the package. The pins go
through holes on a printed circuit board. I/O lead counts as high as 600 can be achieved
with PGA packaging designs.
Pattern-Generation Tape. Computerized instructions used to build
photomasks.
See optical coupler.
Lithographic techniques involving light as the pattern transfer medium. See lithography.
A light-sensitive liquid that is spread as a uniform thin film on a wafer or substrate.
After baking to solidify the liquid, exposure of specific patterns is performed using a
photomask. Material remaining after development shields regions of the wafer from
subsequent etch or implant operations.
The center-to-center spacing between pads, rows of bumps, pins, posts, leads, etc., on
an IC or circuit board.
The act of placing the physical representations of the circuit functions, either as
macro blocks or as rows of standard cells. The signal paths are then routed on the
interconnect layers. Currently, two layers of routing are used, with three layers being
the next step.
Plastic Leaded Chip Carrier. A leaded quad package--a
replacement for the plastic DIP (dual in-line package) in surface-mount applications.
External connections consist of leads around all four sides of the package.
P-channel MOS. A type of MOSFET where the semiconductor channel is doped
P-type. In such a MOSFET, the current between source and drain is primarily due to the
motion of holes. Compare NMOS.
The basic structure formed by the intimate contact of P-type and N-type semiconductors.
The important characteristic of a P-N junction is that it will conduct electric current
with one polarity of applied voltage (forward bias) but will not conduct with the opposite
polarity (reverse bias).
A semiconductor junction transistor with a P-type collector and emitter, and an N-type
base. In such a device, the current amplification arises from the injection of holes from
the emitter into the base, and their subsequent collection in the collector. See bipolar transistor and complementary.
Compare NPN transistor.
- Circuits with the capability of interfacing higher voltages and current levels than
conventional BiMOS circuits. See BiMOS.
- An advanced Intersil wafer process that combines analog, digital and power capabilities
in a single IC. This Double-Layer-Metal (DLM) process is being developed in Findlay, Ohio.
It features complementary vertical MOS power output transistors and 16V operation to
support commercial and industrial applications in plastic packages. See DLM.
System power supply control functions and output drive, allowing electronic systems to
do actual work for such diverse applications as motors, video, and computer disk drives.
Examples of Intersil power control ICs are voltage regulators, rectifiers, and high
current drivers.
See discrete device and intelligent discrete.
A MOSFET circuit capable of handling current ratings of more than 1 ampere. Intersil
power MOSFETs have current-handling capabilities as high as 100A and voltage-handling
capabilities up to 1200V. See MOSFET.
A transistor capable of being used at current ratings of more than 1 ampere. Intersil
bipolar and MOS power transistors have current handling capabilities up to 100A and
voltage handling capabilities to 1200V.
Plastic Quad Flat Pack. A type of plastic package that has
leads on all four sides.
A circuit in which the wires or components have been replaced by a conductive pattern
printed upon or bonded to the surface of an insulating board.
Programmable Read-Only Memory. A read-only memory that can
be written to only once. Programmed after manufacture by external equipment. Typically,
PROMs utilize fusible links that may be burned open to set a specific memory location to a
specific logic level. Intersil invented the PROM, and still markets these devices for
military applications.
Product-To-Market time. The time required to develop a new
product, measured from the initiation of a development program to product introduction.
A semiconductor type in which the density of electrons in the conduction band is
exceeded by the density of holes in the valence band. P-type behavior is induced by the
addition of acceptor impurities, such as boron, to the crystal structure of silicon. See
also acceptors, dopants, donors and impurities.
Physical Vapor Deposition. A process
for depositing a thin film on a wafer that involves aiming a stream of gas at a target.
Secondary emission releases material from the target which is then deposited on the wafer.
This process is also know as sputtering.
Pulse-Width Modulation. A form of analog control in which the
duration of digital pulses is varied analogously with the signal of interest.
